Fourth Workshop on Computer Architecture Research with RISC-V (CARRV 2020)

Virtual Workshop, Friday, May 29th, 2020, Co-located with ISCA 2020

The Fourth Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:

CARRV Invited Talk

CHERI-RISC-V – A Full Stack Solution Mitigating Spatial and Temporal Memory Vulnerabilities
Simon Moore (University of Cambridge)

Originally prototyped on MIPS, we have now added CHERI security extensions to the RISC-V ISA, with multiple open-source cores with various microarchitectures prototyped on FPGA. CHERI extensions for RISC-V provide low-level hardware primitives for in-memory capabilities that allows software to dramatically improve security by mitigating many spatial and temporal memory safety vulnerabilities. Spatial vulnerabilities like buffer-overflow and buffer-over read are typically eliminated through the compiler and linker capturing more of the programmer’s original intent. Pointers are mapped into in-memory capabilities that include bounds, permissions and have integrity properties. Temporal memory safety mitigates vulnerabilities like use-after-free through revocation of capabilities, offering a major performance improvement over existing techniques like address sanitiser. Capabilities provide the basis for other software mitigations, including control-flow robustness and highly efficient compartmentalisation.

Simon Moore is a Professor of Computer Engineering at the University of Cambridge Department of Computer Science and Technology (previously the Computer Laboratory) in England, where he conducts research and teaching in the general area of computer architecture with particular interests in secure and rigorously-engineered processors and subsystems. Robert Watson and Simon Moore lead the CHERI project in Cambridge.

CARRV Preliminary Program

10:00am - 11:00am EST - Session 1

Welcome and opening remarks

Invited Talk - CHERI-RISC-V – A Full Stack Solution Mitigating Spatial and Temporal Memory Vulnerabilities
Simon Moore (University of Cambridge)
11:00am - 11:30am EST - Session 2

TEE Boot Procedure with Crypto-accelerators in RISC-V Processors
Ckristian Duran (University of Electro-Communications), Trong-Thuc Hoang (University of Electro-Communications), Akira Tsukamoto (National Institute of Advanced Industrial Science and Technology), Kuniyasu Suzaki (National Institute of Advanced Industrial Science and Technology), Cong-Kha Pham (University of Electro-Communications) [paper] [slides] [video]

Experiment on Replication of Side Channel Attack via Cache of RISC-V Berkeley Out-of-order Machine (BOOM) Implemented on FPGA
Anh-Tien Le (The University of Electro-Communications (UEC)), Ba-Anh Dao (The University of Electro-Communications (UEC)), Kuniyasu Suzaki (Technology Research Association of Secure IoT Edge application based on RISC-V Open architecture (TRASIO)), Cong-Kha Pham (The University of Electro-Communications (UEC)) [paper] [slides] [video]

Automatic Code Generation for Rocket Chip RoCC Accelerators
Pengcheng Xu, Yun Liang (Peking University) [paper] [slides] [video]

Efficient Multiple-ISA Embedded Processor Core Design Based on RISC-V
Yuanhu Cheng, Libo Huang, Yijun Cui, Sheng Ma, Yongwen Wang, Bincai Sui (National University of Defense Technology) [paper] [slides] [video]
11:30am - 12:00noon EST - Session 3

PERC: Posit Enhanced Rocket Chip
Arunkumar M V, Sai Ganesh Bhairathi, Harshal Hayatnagarkar (ThoughtWorks Technologies) [paper] [slides] [video]

Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation
Xuan Guo, Robert Mullins (University of Cambridge) [paper] [slides] [video]

A RISC-V SystemC-TLM simulator
Màrius Montón (Universitat Autònoma de Barcelona) [paper] [slides] [video]

Enabling Hardware Randomization Across the Cache Hierarchy in Linux-Class Processors
Max Doblas Font (Barcelona Supercomputing Center (BSC)), Ioannis-Vatistas Kostalabros (Barcelona Supercomputing Center (BSC)), Miquel Moretó Planas (Barcelona Supercomputing Center (BSC)), Carles Hernández Luz (Universitat Politècnica de València) [paper] [slides] [video]
12:00noon - 12:30pm EST - Session 4

Recommendations for a Radically Secure ISA
Mathieu Escouteloup (Inria, Univ Rennes, CNRS, IRISA), Jacques Fournier (Univ. Grenoble Alpes, CEA Leti, DSYS/LSOSP), Jean-Louis Lanet (LHS-PEC), Ronan Lashermes (Inria/SED&LHS) [paper] [slides] [video]

Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core
Nils Wistoff (ETH Zürich), Moritz Schneider (ETH Zürich), Frank K. Gürkaynak (ETH Zürich), Luca Benini (ETH Zürich), Gernot Heiser (UNSW and Data61 CSIRO) [paper] [slides] [video]

Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator
Nikolaos Charalampos Papadopoulos, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris and Dionisios Pnevmatikatos (National Technical University of Athens) [paper] [slides] [video]

HW/SW Approaches for RISC-V Code Size Reduction
Matteo Perotti (ETH Zürich), Pasquale Davide Schiavone (ETH Zürich), Giuseppe Tagliavini (University of Bologna), Davide Rossi (University of Bologna), Tariq Kurd (Huawei), Mark Hill (Huawei), Liu Yingying (Huawei), Luca Benini (ETH Zürich and University of Bologna) [paper] [slides] [video]
12:30pm - 1:00pm EST - Session 5

Software-Based Off-Chip Memory Protection for RISC-V Trusted Execution Environments
Gui Andrade, Dayeol Lee, David Kohlbrenner, Krste Asanović, Dawn Song (University of California, Berkeley) [paper] [slides] [video]

Ariane + NVDLA: Seamless Third-Party IP Integration with ESP
Davide Giri (Columbia University), Kuan-Lin Chiu (Columbia University), Guy Eichler (Columbia University), Paolo Mantovani (Columbia University), Nandhini Chandramoorthy (IBM Thomas J. Watson Research Center), Luca P. Carloni (Columbia University) [paper] [slides] [video]

SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine
Jerry Zhao, Ben Korpan, Abraham Gonzalez and Krste Asanović (University of California, Berkeley) [paper] [slides] [video]

Closing remarks

Important Dates

Virtual Workshop Information (updated)

The ISCA 2020 conference, as well as all workshops and tutorials, will be taking place virtually this year. The new workshop format now includes all presentations and papers being immediately available online for viewing. During the live workshop session, all authors will first present a short lightning-talk overview of their work, followed by answering a selection of questions during a Q&A session. During the week leading up to the workshop, registered attendees will be able to discuss and vote on questions for the authors to address. Vote on or contribute your own questions for the authors, as only top questions will be selected for response. ISCA Registration will open on May 25th, and registration is necessary to vote for questions and attend the live session on May 29th. If you still want to submit a question, but the sessions have already started, feel free to use the Q&A function of Zoom.


Submission Guidelines

All papers should be submitted electronically by EasyChair. Submissions in PDF format must be limited to 6 pages including figures and tables, plus as many pages as needed for references. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.

Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here.

Note: Workshop publications do not preclude publishing at future conference venues.


All questions about submissions can be emailed to Arun Thomas «».