Second Workshop on Computer Architecture Research with RISC-V (CARRV 2018)

Los Angeles, CA, USA, June 2, 2018, Co-located with ISCA 2018

The Second Workshop on Computer Architecture Research with RISC-V (CARRV) brings together researchers in fields related to computer architecture, compilers, and systems for technical exchange on using RISC-V in computer architecture research. Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:

The workshop is intended to be highly interactive with an open session discussing experiences with using the current state of the RISC-V ecosystem for architecture research and what directions to take to improve it.

CARRV Program

8:30am - 9am
Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems
Schuyler Eldridge, Alper Buyuktosunoglu, Pradip Bose (IBM T. J. Watson Research Center) [paper] [slides]

9am - 9:30am
Flexible Timing Simulation of RISC-V Processors with Sniper
Neethu Bal Mallya (National University of Singapore, Singapore), Cecilia Gonzalez-Alvarez (Ghent University, Belgium), Trevor E. Carlson (National University of Singapore, Singapore) [paper] [slides]

9:30am - 10:00am
Implementation of Direct Segments on a RISC-V Processor
Nikhita Kunati, Michael M. Swift (University of Wisconsin-Madison) [paper] [slides]
10:00am - 10:30am
10:30am - 11:00am
A Formally Verified Cryptographic Extension to a RISC-V Processor
Joseph R. Kiniry (Galois, Inc.), Daniel M. Zimmerman (Galois, Inc.), Robert Dockins (Galois, Inc.) and Rishiyur Nikhil (Bluespec, Inc.) [paper] [slides]

11:00am - 11:30am
Designing Digital Signal Processors with RocketChip
Paul Rigge, Borivoje Nikolić (University of California, Berkeley) [paper] [slides]

11:30am - 12:00pm
Automating the Area-Delay Trade-off Problem
Haven Skinner, Rafael Trapani Possignolo, Jose Renau (UCSC) [paper] [slides]
12:00pm - 1:30pm
1:30pm - 2:00pm
Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud
Donggyu Kim (University of California, Berkeley), Christopher Celio (Esperanto Technologies), Sagar Karandikar (University of California, Berkeley), David Biancolin (University of California, Berkeley), Jonathan Bachrach (University of California, Berkeley), Krste Asanovic (University of California, Berkeley) [paper]

2:00pm - 2:30pm
Simulating Multi-Core RISC-V Systems in gem5
Tuan Ta, Lin Cheng, Christopher Batten (Cornell University) [paper]
2:30pm - 3:30pm
Panel Discussions

Important Dates


Submission Guidelines

All papers should be submitted electronically by EasyChair. Submissions in PDF format must be limited to 6 pages including figures and tables, plus as many pages as needed for references. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.

Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here.

Note: Authors may submit to both CARRV and the 8th RISC-V Workshop, but please remember that CARRV has an explicit research focus.

Note: Workshop publications do not preclude publishing at future conference venues.


All questions about submissions can be emailed to Arun Thomas «».