First Workshop on Computer Architecture Research with RISC-V (CARRV 2017)

Boston, MA, USA, October 14, 2017, Co-located with MICRO 2017

The First Workshop on Computer Architecture Research with RISC-V (CARRV) brings together researchers in fields related to computer architecture, compilers, and systems for technical exchange on using RISC-V in computer architecture research. Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:

The workshop is intended to be highly interactive with an open session discussing experiences with using the current state of the RISC-V ecosystem for architecture research and what directions to take to improve it.

CARRV Program

8:30am - 9am
Computer Architecture Research with RISC-V
Krste Asanovic (University of California, Berkeley). [slides]
9am - 9:25am
Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
Tutu Ajayi (University of Michigan), Khalid Al-Hawaj (Cornell University), Aporva Amarnath (University of Michigan), Steve Dai (Cornell University), Scott Davidson (University of California, San Diego), Paul Gao (University of California, San Diego), Gai Liu (Cornell University), Anuj Rao (University of California, San Diego), Austin Rovinski (University of Michigan), Ningxiao Sun (University of California, San Diego), Christopher Torng (Cornell University), Luis Vega (University of Washington), Bandhav Veluri (University of California, San Diego), Shaolin Xie (University of California, San Diego), Chun Zhao (University of California, San Diego), Ritchie Zhao (Cornell University), Christopher Batten (Cornell University), Ronald Dreslinski (University of Michigan), Rajesh Gupta (University of California, San Diego), Michael Taylor (University of Washington) and Zhiru Zhang (Cornell University) [paper] [slides]

9:25am - 9:50am
A Low Voltage RISC-V Heterogeneous System
Schuyler Eldridge (IBM T. J. Watson Research), Karthik Swaminathan (IBM T. J. Watson Research), Nandhini Chandramoorthy (IBM T. J. Watson Research), Alper Buyuktosunoglu (IBM T. J. Watson Research), Alec Roelke (University of Virginia), Xinfei Guo (University of Virginia), Vaibhav Verma (University of Virginia), Rajiv Joshi (IBM T. J. Watson Research), Mircea Stan (University of Virginia) and Pradip Bose (IBM T. J. Watson Research) [paper] [slides]

9:50am - 10:15am
BOOMv2: an open-source out-of-order RISC-V core
Christopher Celio (University of California, Berkeley), Pi-Feng Chiu (University of California, Berkeley), Borivoje Nikolic (University of California, Berkeley), David Patterson (University of California, Berkeley) and Krste Asanovic (University of California, Berkeley) [paper] [slides]

10:15am - 10:40am
Diplomatic Design Patterns: A TileLink Case Study
Henry Cook (SiFive), Wesley Terpstra (SiFive) and Yunsup Lee (SiFive) [paper] [slides]
10:40am - 11am
11am - 11:25am
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
Andreas Kurth (ETH Zurich), Pirmin Vogel (ETH Zurich), Andrea Marongiu (ETH Zurich), Alessandro Capotondi (University of Bologna) and Luca Benini (ETH Zurich) [paper] [slides]

11:25am - 11:40am
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Framework, and a 1680-core, 26 MB SRAM Parallel Processor Overlay on Xilinx UltraScale+ VU9P
Jan Gray (Gray Research) [paper] [slides]

11:40am - 12:05pm
Taiga: A Configurable RISC-V soft-processor framework for Heterogeneous Computing Systems Research
Eric Matthews (Simon Fraser University) and Lesley Shannon (Simon Fraser University) [paper] [slides]
12:05pm - 1pm
1pm - 1:25pm
A RISC V Extension for the Fresh Breeze Architecture
Jack Dennis (MIT) and Willie Lim (MIT) [paper] [slides]

1:25pm - 1:50pm
Simty: generalized SIMT execution on RISC-V
Sylvain Collange (INRIA) [paper] [slides]

1:50pm - 2:05pm
Building Hardware Components for Memory Protection of Applications on a Tiny Processor
Hyunyoung Oh (Seoul National University), Yongje Lee (Seoul National University), Junmo Park (Seoul National University), Myonghoon Yang (Seoul National University) and Yunheung Paek (Seoul National University) [paper] [slides]

2:05pm - 2:20pm
Labeled RISC-V: A New Perspective on Software-Defined Architecture
Zihao Yu (Chinese Academy of Sciences), Bowen Huang (Chinese Academy of Sciences), Jiuyue Ma (Chinese Academy of Sciences), Ninghui Sun (Chinese Academy of Sciences) and Yungang Bao (Chinese Academy of Sciences) [paper] [slides]

2:20pm - 2:35pm
RV-IOV: Tethering RISC-V Processors via Scalable I/O Virtualization
Luis Vega (University of Washington) and Michael Taylor (University of Washington) [paper] [slides]

2:35pm - 3pm
Evaluation of RISC-V RTL Designs with FPGA Simulation
Donggyu Kim (University of California, Berkeley), Christopher Celio (University of California, Berkeley), David Biancolin (University of California, Berkeley), Jonathan Bachrach (University of California, Berkeley) and Krste Asanovic (University of California, Berkeley) [paper] [slides]
3pm - 3:30pm
3:30pm - 3:55pm
Full-System Simulation of Java Workloads With RISC-V and the Jikes Research Virtual Machine
Martin Maas (University of California, Berkeley), Krste Asanovic (University of California, Berkeley) and John Kubiatowicz (University of California, Berkeley) [paper] [slides]

3:55pm - 4:20pm
rv8: a high performance RISC-V to x86 binary translator
Michael Clark (rv8) and Bruce Hoult (rv8) [paper] [slides]

4:20pm - 4:45pm
RISC5: Implementing the RISC-V ISA in gem5
Alec Roelke (University of Virginia) and Mircea Stan (University of Virginia) [paper] [slides]
4:45pm - 5:30pm
Open Discussion - Current State of RISC-V for Research


Important Dates

Submission Guidelines

All papers should be submitted electronically by EasyChair. Submissions must be limited to 6 pages including figures and tables, plus as many pages as needed for references. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.

Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here.

Note: Authors may submit to both CARRV and the 7th RISC-V Workshop, but please remember that CARRV has an explicit research focus.

Note: Workshop publications do not preclude publishing at future conference venues.


All questions about submissions can be emailed to Arun Thomas «».