Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019)

Phoenix, AZ, USA, June 22, 2019, Co-located with ISCA 2019

The Third Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:

CARRV Preliminary Program

9:00am - 9:30am
OpenPiton+Ariane: The First SMP Linux-booting RISC-V System Scaling from One to Many Cores
Jonathan Balkind (Princeton University), Michael Schaffner (ETH Zurich), Katie Lim (Princeton University), Florian Zaruba (ETH Zurich), Fei Gao (Princeton University), Jinzheng Tu (Princeton University), David Wentzlaff (Princeton University) and Luca Benini (ETH Zurich) [paper]

9:30am - 10:00am
Replicating and Mitigating Spectre Attacks on a Open Source RISC-V Microarchitecture
Abraham Gonzalez, Ben Korpan, Jerry Zhao, Ed Younis and Krste Asanović (University of California, Berkeley) [paper]

10:00am - 10:30am
Finger Finder: A Low-Energy Peak Detection Accelerator for Capacitive Touch Controllers
Kai Kristian Amundsen (MyWo AS), Gaute Myklebust (MyWo AS), Per Gunnar Kjedsberg (Norwegian University of Science and Technology) and Magnus Jahre (Norwegian University of Science and Technology) [paper] [slides]

10:30am - 11:00am
Vortex RISC-V GPGPU system: Extending the ISA, Synthesizing the Microarchitecture, and Modeling the Software Stack
Fares Elsabbagh, Bahar Asgari, Hyesoon Kim and Sudhakar Yalamanchili (Georgia Institute of Technology) [paper]
11:00am - 11:30am
11:30am - 12:00am
Variable Precision Floating-Point RISC-V Coprocessor Evaluation using Lightweight Software and Compiler Support
Tiago T. Jost (CEA, LETI, Univ. Grenoble Alpes), Andrea Bocco (CEA, LETI, Univ. Grenoble Alpes), Yves Durand (CEA, LETI, Univ. Grenoble Alpes), Christian Fabre (CEA, LETI, Univ. Grenoble Alpes), Florent de Dinechin (INSA) and Albert Cohen (Google) [paper]

12:00am - 12:30pm
IEEE Floating-Point Extensions for Containing Error in the RISC-V Architecture
Alexander Underwood, Tuan Nguyen and James Stine (Oklahoma State University) [paper]
12:30pm - 2:00pm
2:00pm - 2:30pm
Invited Talk - Federation: An Open-Source Chip Design Workflow
Henry Cook and Yunsup Lee (SiFive) [slides]

2:30pm - 3:00pm
Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research
Sagar Karandikar, David Biancolin, Alon Amid, Nathan Pemberton, Albert Ou, Randy Katz, Borivoje Nikolić, Jonathan Bachrach and Krste Asanović (University of California, Berkeley) [paper]

3:00pm - 3:30pm
Fast TLB Simulation for RISC-V Systems
Xuan Guo and Robert Mullins (University of Cambridge) [paper] [slides]
3:30pm - 4:00pm
4:00pm - 4:30pm
Towards Deep Learning using TensorFlow Lite on RISC-V
Marcia Sahaya Louis (Boston University), Zahra Azad (Boston University), Leila Delshadtehrani (Boston University), Suyog Gupta (Google), Pete Warden (Google), Vijay Janapa Reddi (Harvard University) and Ajay Joshi (Boston University) [paper]

4:30pm - 5:00pm
Nested-Parallelism PageRank on RISC-V Vector Multi-Processors
Alon Amid, Albert Ou, Krste Asanović and Borivoje Nikolić (University of California, Berkeley) [paper]

Important Dates


Submission Guidelines

All papers should be submitted electronically by EasyChair. Submissions in PDF format must be limited to 6 pages including figures and tables, plus as many pages as needed for references. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.

Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here.

Note: Workshop publications do not preclude publishing at future conference venues.


All questions about submissions can be emailed to Arun Thomas «».