Located at the Union Square conference room (lower level)
The Sixth Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and security evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:
Hardware Support for Managed Languages: An Old Idea Whose Time Has Finally Come?
Martin Maas (Google Research, Google Brain)
A large number of workloads are written in managed languages, including server workloads in data centers, web applications in browsers, and client workloads on desktops or mobile devices. Due to their widespread adoption, improving the performance and efficiency of managed-language features such as garbage collection, JIT compilation, and dynamic runtime checks can have a significant impact on many real workloads. Hardware support for such features has been investigated since the 1970s, but still has not seen widespread practical adoption.
In this talk, I will discuss trends that make today a great time to revisit these ideas. I will describe work done at UC Berkeley that moves garbage collection into a small hardware accelerator close to the memory controller and performs GC more efficiently than a CPU. I will also talk about current work within the open-source RISC-V project on developing standard extensions for managed-language support in the context of the free and open RISC-V ISA. Finally, I will lay out opportunities for research in this area, and how open-source infrastructure can be used to build end-to-end prototypes of this work in an academic setting.
Martin Maas is a Staff Research Scientist at Google Research and part of the Google Brain team. His research interests are in language runtimes, computer architecture, systems, and machine learning, with a focus on applying machine learning to systems problems. He also chairs the J Extension group within the RISC-V project, which investigates managed-runtime extensions. Before joining Google, Martin completed his PhD in Computer Science at the University of California at Berkeley, where he worked on hardware support for managed languages and architectural support for memory-trace obliviousness (both based on RISC-V).
9:00am - 10:30am EST - Session 1 - Platforms, Testing and Simulation
Welcome and opening remarks
Architecture and RISC-V ISA Extension Supporting Asynchronous and Flexible Parallel Far Memory Access
Songyue Wang, Luming Wang, Tianyue Lu, Mingyu Chen (Institute of Computing Technology, Chinese Academy of Sciences) [paper] [slides]
The Case for Using Guix to Enable Reproducible RISC-V Software & Hardware
Christopher Batten (Cornell University), Pjotr Prins, Efraim Flashner, Arun Isaac (The University of Tennessee Health Science Center), Jan van Nieuwenhuizen (Joy of Source), Ekaitz Zarraga (ElenQ Technologies), Tuan Ta, Austin Rovinski (Cornell University), Erik Garrison (The University of Tennessee Health Science Center) [paper]
Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V
S Pawan Kumar (InCore Semiconductors), Shrreya Singh (IIT Gandhinagar), Neel Gala (InCore Semiconductors), Allen Baum (Esperanto Technologies) [paper] [slides]
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP
Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. Carloni (Columbia University) [paper] [slides]
Open-Source RISC-V Linux-Compatible NVMM Emulator
Yu Omori, Keiji Kimura (Waseda University) [paper]
|10:30am - 11:00am EST - Coffee Break|
11:00am - 12:00noon EST - Invited Talk
Invited Talk - Hardware Support for Managed Languages: An Old Idea Whose Time Has Finally Come?
Martin Maas (Google Research, Google Brain)
|12:00noon - 1:30am EST - Lunch|
1:30pm - 2:30pm EST - Session 2 - Security and Cryptography
AOS-RISC-V: Towards Always-On Heap Memory Safety
Yonghae Kim, Anurag Kar, Siddant Singh, Ammar A. Ratnani (Georgia Tech), Jaekyu Lee (Arm Research, Intel), Hyesoon Kim (Georgia Tech) [paper] [slides]
Protection and Relocation Extension for RISC-V
Maja Malenko, Leandro Batista Ribeiro, Marcel Baunach (Graz University of Technology) [paper]
HYDRA: A Multi-core RISC-V with Cryptographically Useful Modes of Operation
Ben Marshall (PQShield), Dan Page, Thinh Pham, Max Whale (University of Bristol) [paper] [slides]
|2:30pm - 3:30pm EST - Coffee Break|
3:30pm - 4:30pm EST - Session 3 - Acceleration and Extensions
RISC-V Instruction Set Extension for Graph Applications
Mehmetali Semi Yenimol, Gülce Pulat, Ozcan Ozturk (Bilkent University) [paper]
Shared Vector Register of RISC-V for the Future Hardware Acceleration
Tomoaki Tanaka, Ryosuke Higashi, Hidetaro Tanaka (Tokyo University of Agriculture and Technology), Takefumi Miyoshi (WasaLabo, LLC.), Yasunori Osana (University of the Ryukyus), Jubee Tada (Graduate School of Science and Engineering, Yamagata University), Kiyofumi Tanaka (Japan Advanced Institute of Science and Technology), Hironori Nakajo (Tokyo University of Agriculture and Technology) [paper]
Implementing Hardware Extensions for Multicore RISC-V GPUs
Tine Blaise, Hyesoon Kim (Georgia Institute of Technology) [paper]
The ISCA 2022 conference organizers have informed us that ISCA 2022, and the workshops and tutorials, will take place in-person this year.
All papers should be submitted electronically to HotCRP. Submissions in PDF format must be limited to 6 pages including figures and tables, plus as many pages as needed for references. Papers must be in PDF format and the submission should be anonymous.
Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here.
Note: Workshop publications do not preclude publishing at future conference venues.
All questions about submissions can be emailed to: schirice at ieee dot org.