The Eighth Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and evaluation of RISC-V cores, SoCs, and accelerators. The topics of specific interest for the workshop include, but are not limited to:
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8:30am - 9:30am CST
Welcome and opening remarks Invited Talk - Pre-silicon Side-channel Leakage Assessment Across the Hardware/Software Boundary Patrick Schaumont (Worcester Polytechnic Institute (WPI)) AbstractSide-channel leakage assessment is a crucial but challenging verification step for programmable systems that manage secure assets. A pre-silicon design method based on power modeling can significantly reduce the likelihood of side-channel design flaws. However, such an approach requires a comprehensive system model to bridge the gap between high-level secure software assets and the physical side-channel leakage in hardware. The trade-off between model accuracy and simulation performance is difficult, because more detailed models become less practical due to their simulation complexity. To address this challenge, we propose a top-down hierarchical pre-silicon side-channel leakage assessment methodology that spans three modeling levels commonly used in System-on-Chip design: architecture-level, microarchitecture-level, and gate-level. We classify side-channel leakage sources across these abstraction levels and show that each level introduces unique power-based leakage characteristics. Our hierarchical approach enables systematic debugging of side-channel vulnerabilities from higher abstraction levels down to lower ones. The methodology is illustrated with practical examples from a System-on-Chip design, demonstrating various cases of side-channel bugs and their resolution. |
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9:30am - 10:00am CST
GPGPU Pipeline Visualization for RISC-V SIMT Architecture Yu-Yu Hsiao, Liang-Chou Chen, Chung-Ho Chen (National Cheng Kung University) [paper] [slides] |
| 10:00am - 10:30am CST - Coffee Break |
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10:30am - 11:00am CST
Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension George-Marios Fragkoulis, Nikos Karystinos, George Papadimitriou, Dimitris Gizopoulos (University of Athens) [paper] [slides] |
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11:00am - 12:00pm CST
Invited Talk - Hardware Fuzzing: What? Why? How? Jeyavijayan "JV" Rajendran (Texas A&M University) AbstractHardware is at the heart of computing systems. However, recent years have seen increased attacks exploiting hardware vulnerabilities and exploits, which even traditional software-based protections cannot prevent. Hardware fuzzing has shown promise in detecting vulnerabilities in large-scale designs like modern processors. In this talk, I will describe the hardware vulnerabilities in hardware description languages, such as Verilog and VHDL. Then, I will explain a new and radical approach called hardware fuzzing to find these vulnerabilities and detail how fuzzing techniques can be combined with existing formal verification techniques to detect vulnerabilities efficiently. Finally, I will discuss a strategy for pinpointing vulnerabilities to accelerate the mitigation process and briefly talk about improving the efficiency of hardware fuzzing using ML/AI techniques, such as multi-armed bandit (MAB) and large language models (LLM). |
| 12:00pm - 1:00pm CST - Lunch |
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1:00pm - 1:30pm CST
Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency Hansung Kim, Ruohan Yan, Joshua You, Tieliang Vamber, Yakun Sophia Shao (University of California, Berkeley) [paper] [slides] |
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1:30pm - 2:00pm CST
Extending RISC-V Keystone to Include Efficient Secure Memory Tamara Lehman and Zach Moolman (University of Colorado Boulder) [paper] [slides] |
All papers should be submitted electronically to EasyChair. Submissions in PDF format must be limited to 6 pages including figures and tables, plus as many pages as needed for references. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.
Papers must be formatted in accordance with the ACM two column style. ACM Word or LaTeX style templates are available here.
Note: Workshop publications do not preclude publishing at future conference venues.
The submissions should be done via EasyChair
All questions about submissions can be emailed to: komail dot dharsee+carrv at gmail dot com