The Fifth Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:
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9:00am - 9:30am EST - Session 1, Design 1
Welcome and opening remarks RISKA: Towards an Open-source RISC-V based Domain-specific System-on-Chip for SKA Data Processing Arunkumar M V, Harshal G. Hayatnagarkar (ThoughtWorks Technologies, India) [paper] [slides] [video] [discussions] NeuralScale: A RISC-V Based Neural Processor Boosting AI Inference in Clouds Rongkai Zhan, Xiaobo Fan (Stream Computing Inc.) [paper] [slides] [video] [discussions] RISC-V Dataflow Extension Martin Cowley, Lina Sawalha (Western Michigan University) [paper] [slides] [video] [discussions] Versatile RISC-V ISA Galois Field arithmetic extension for cryptography and error-correction codes Yao-Ming Kuo, Francisco Garcia Herrero, Juan Antonio Maestro (Antonio de Nebrija University) [paper] [slides] [video] [discussions] |
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9:30am - 10:00am EST - Session 2, Analysis
Performance Counter Design Variation in Rocket Chip via Feature-Oriented Programming Justin Deters, Ron Cytron (Washington University in St. Louis) [paper] [slides] [video] [discussions] Supporting RISC-V Performance Counters through Performance analysis tools for Linux (Perf) Joao Mario Domingos, Pedro Tomás, Leonel Sousa (INESC-ID, Instituto Superior Técnico, Universidade de Lisboa) [paper] [slides] [video] [discussions] Towards Accurate Performance Modeling of RISC-V Designs Odysseas Chatzopoulos, George-Marios Fragkoulis, George Papadimitriou, Dimitris Gizopoulos (University of Athens) [paper] [slides] [video] [discussions] From Swift to Mighty: A Cost-Benefit Analysis of Ibex and CV32E40P Regarding Application Performance, Power and Area Noam Gallmann (ETH Zürich), Pirmin Vogel (lowRISC C.I.C.), Pasquale Davide Schiavone (OpenHW Group), Luca Benini (ETH Zürich, University of Bologna) [paper] [slides] [video] [discussions] |
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10:00am - 10:30am EST - Session 3, Security 1
Introducing Fast and Secure Deterministic Stash Free Write Only Oblivious RAMs for Demand Paging in Keystone Mriganka Shekhar Chakravarty (IIT Kanpur), Biswabandan Panda (IIT Bombay) [paper] [slides] [video] [discussions] Developing a Test Suite for Transient-Execution Attacks on RISC-V and CHERI-RISC-V Franz A. Fuchs, Jonathan Woodruff, Simon W. Moore (University of Cambridge), Peter G. Neumann (SRI International), Robert N. M. Watson (University of Cambridge) [paper] [slides] [video] [discussions] Secure Speculative Execution via RISC-V Open Hardware Design Majid Sabbagh, Yunsi Fei, David Kaeli (Northeastern University) [paper] [slides] [video] [discussions] Cryptography Acceleration in a RISC-V GPGPU Austin Adams, Pulkit Gupta, Blaise Tine, Hyesoon Kim (Georgia Institute of Technology) [paper] [slides] [video] [discussions] |
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10:30am - 11:00am EST - Session 4, Simulation and Verification
Supporting RISC-V Full System Simulation in gem5 Peter Yuen Ho Hin, Xiongfei Liao, Jin Cui, Andrea Mondelli, Thannirmalai Muthukaruppan Somu, Naxin Zhang (Huawei Research Centre) [paper] [slides] [video] [discussions] Leveraging RISC-V to build an open-source (hardware) OS framework for reconfigurable IoT devices Miguel Silva, Tiago Gomes, Sandro Pinto (Centro ALGORITMI, University of Minho) [paper] [slides] [video] [discussions] A Flexible Uncore Infrastructure for RISC-V Core Development Michael Jungmair, Tobias Schmidt, Alexis Engelke, Armin Ettenhofer, Felix Krayer, Jonas Lauer, Malte von Ehren, Martin Schulz (Technical University of Munich) [paper] [slides] [video] [discussions] rtlv: push-button verification of software on hardware Noah Moroze, Anish Athalye, Frans Kaashoek, Nickolai Zeldovich (MIT CSAIL) [paper] [slides] [video] [discussions] |
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11:00am - 11:30am EST - Session 5, Design 2
Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk (Imperial College London) [paper] [slides] [video] [discussions] Supporting CUDA for an extended RISC-V GPU architecture Ruobing Han, Blaise Tine, Jaewon Lee (Georgia Institute of Technology), Jaewoong Sim (Seoul National University), Hyesoon Kim (Georgia Institute of Technology) [paper] [slides] [video] [discussions] Arrow: A RISC-V Vector Accelerator for Machine Learning Inference Imad Al Assir, Mohamad El Iskandarani, Hadi Rayan Al Sandid, Mazen A. R. Saghir (American University of Beirut) [paper] [slides] [video] [discussions] Bringing OpenCL to Commodity RISC-V CPUs Tine Blaise (Georgia Tech), Seyong Lee, Jeff Vetter (Oak Ridge National Laboratory), Hyesoon Kim (Georgia Tech) [paper] [slides] [video] [discussions] |
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11:30am - 12:00noon EST - Session 6, Security 2
RISC-V Microarchitecture Simulation State Enumeration Griffin Knipe, Derek Rodriguez, Yunsi Fei, David Kaeli (Northeastern University) [paper] [slides] [video] [discussions] Enabling Design Space Exploration for RISC-V Secure Compute Environments Ayaz Akram, Venkatesh Akella (University of California, Davis), Sean Peisert (Lawrence Berkeley National Laboratory), Jason Lowe-Power (University of California, Davis) [paper] [slides] [video] [discussions] ERTOS: Enclaves in Real-Time Operating Systems Alexander Thomas, Stephan Kaminsky, Dayeol Lee, Dawn Song, Krste Asanovic (University of California, Berkeley) [paper] [slides] [video] [discussions] Closing remarks |
The ISCA 2021 conference organizers have informed us that ISCA 2021, and the workshops and tutorials, will take place virtually this year. In addition, the workshops will take place after the ISCA conference.
All papers should be submitted electronically to HotCRP. Submissions in PDF format must be limited to 6 pages including figures and tables, plus as many pages as needed for references. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.
Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here.
Note: Workshop publications do not preclude publishing at future conference venues.
All questions about submissions can be emailed to Silviu Chiricescu «schirice@ieee.org».